Conventionally, some memories such as DRAMs in semiconductor devices include fuses so as to cause redundancy bits replacing defective bits to function (refer to Nonpatent Document 1, for example). The operation of the semiconductor device is checked after a wafer manufacturing process thereof, and if a defective bit is detected, a laser is irradiated onto a fuse connected to the defective bit for disconnection, so as to replace the defective bit with a redundancy bit.
As the method of using fuses in the semiconductor device, there is provided a method as follows, in addition to the method in case of the memory. Assume that recording of information “1” or “0” is performed, responsive to a state where the fuse is disconnected or not. Then, by providing 128 fuses for each semiconductor chip, for example, information corresponding to 128 bits can be recorded on each semiconductor chip. If the information to be recorded is an identifier that differs from one semiconductor chip to another, by reading the information recorded for the fuse, each semiconductor chip becomes distinguishable.
As other method of using fuses, there is provided a semiconductor device in which fuses for voltage adjustment in the semiconductor device is provided, an internal voltage is measured after the wafer manufacturing process, and then certain fuse or fuses is/are disconnected to obtain a desired voltage.
A configuration of the semiconductor device in case of Non patent Document 1 is explained below.
FIG. 5 is a schematic sectional view showing an example of the configuration of the conventional semiconductor device.
In this semiconductor device, semiconductor elements (not shown) such as transistors, capacitors, and resistances and a base insulating film 101 are formed on a semiconductor substrate 100. Then, as shown in FIG. 5, copper (Cu) wiring (connection) 120 is formed in a SiO2 film 102 formed as an insulating film for embedding of wiring, and Al (aluminum) wiring (connection) 124 is formed on the Cu wiring 120. An interlayer insulating film between the Cu wiring 120 and the Al wiring 124 for portions other than a connecting portion between the Cu wiring 120 and the Al wiring 124 is a single layer SiO2 film 210. Further, a fuse 122 is covered with a SiO2 film 210. The formed film thickness of the SiO2 film 210 is approximately 1 μm. A SiON film 212 is formed on the SiO2 film 210, and its film thickness is approximately 1 μm.
The fuse 122 is connected to the circuit through wiring not shown. The fuse 122 is also formed at the same layer as a Cu corrosion preventive film 123, and is a multilayer conductive film formed by sequentially stacking Ti and TiN films, which will be hereinafter written as a “TiN/Ti structure”.
While the Al wiring 124 in FIG. 5 serves as a bonding pad section 126, other Al wiring (not shown) formed at the same layer as the Al wiring 124 serves to establish electrical connection between elements.
When openings for bonding shown in FIG. 5 are formed, the time for etching the SiO2 film 210 was controlled to leave only a predetermined film thickness of the SiO2 film 210 on the fuse 122.
[Non Patent Document 1]
K. Arndt et al., Reliability of Laser Activated Metal Fuses in DRAMS, 1999 JEEE/CPMT Int'1 Electronics Manufacturing Technology Symposium, p. 389-394